CPUs contain in addition to their fetch and execute circuitry for fetching and executing instructions from a memory, an instruction pointer register which holds the address in memory of an instruction to be executed by the CPU. Knowledge of the address held in the instruction pointer register is of particular importance when performing diagnostic functions on software which is running on a CPU. In some, simple, cases, the address held as the instruction pointer can be deduced by observing the memory address value on an external memory bus. However, in many cases the instruction pointer is hidden within the depths of the CPU and is not readily accessible outside the CPU.
In particular, in the past CPUs were manufactured as a single chip, requiring off-chip access to all their ancillary circuitry, such as memory. As a result, they had a plurality of access pins so that information about the CPU, in particular memory address information, was in any event externally available from these access pins.
Nowadays, chips are more complex and contain not only a processor on-chip but also its associated memory and other ancillary circuitry. It is no longer a simple matter to monitor the operation of the processor because the signals which are normally available off-chip no longer provide a direct indication as to the internal operation of the CPU.
With the increasing complexity of software designed to run on integrated CPUs, it is increasingly important to adequately test the software. This requires techniques for monitoring operation of the CPU while it executes the software. It is a particularly onerous requirement that the software be monitored non-intrusively while it is operating in real time.
So-called diagnostic or debugging techniques have been developed in an attempt: to achieve this. One of these techniques is to use a logic state analyser (LSA). This is a device connected to the pins of the integrated circuit which monitors continuously the state of all off-chip communications. Each sequentially produced set of states is stored and can then be analysed. Not only is an LSA expensive, but it requires a large amount of deduction and analysis to derive any useful information from the huge number of sequentially produced state sets which are stored. As it is only possible to analyse the status signals being communicated off-chip, it is inevitably necessary to make some deduction or hypothesis concerning the on-chip situation. It is sometimes possible by this technique to deduce instruction pointers. The sequence of addresses stored in the instruction pointer register which is captured by the LSA is referred to as an instruction trace.
Sometimes it is also possible to create an instruction trace in an equivalent virtual environment by software simulation, hardware simulation, hardware emulation or other means. However, none of these techniques reflect the real world situation or real time sequence of events. Such a trace is often useful for comparing against a real time instruction trace, but is otherwise of limited value in diagnostic procedures.
In any event, none of these techniques can be used to find out information concerning the instruction pointer unless it can be deduced by observing external connection pins. If there are no existing external connection pins, external connection pins may sometimes be added specifically to retrieve the instruction pointer from the instruction pointer register. This is an additional overhead to the chip solely for the purpose of debugging. Moreover, in some circumstances even this is not possible.